Formal Verification of VHDL Models

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 19962
Amount: $300,000.00
Phase: Phase II
Program: SBIR
Awards Year: 1994
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
301 Dates Drive, Ithaca, NY, 14850
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Mark Bickford
 (607) 277-2020
Business Contact
Phone: () -
Research Institution
The goal of this project is to create tools to support the formal verification of VHDL designs. Two existing formal verification tools will be enhanced to support VHDL. The first, Spectool, will allow a class of designs, the synchronous finite-state controlled systems, to be specified and verified and then translated into VHDL. This capability will allow VHDL to be used as an interface between Spectool, which has been used to verify several large designs, and other CAD tools. The second tool, Penelope, will be enhanced to allow specification and verification of arbitrary VHDL designs. Phase I will complete the enhancement of Spectool to allow translation of verified designs into VHDL. Examples will be worked using the enhanced tool and will guide the development of the VHDL interface language to be used in the VHDL-enhanced Penelope. Penelope will be enhanced to support the core language constructs of VHDL, laying a foundation for the Phase II effort. In Phase II of the project, the VHDL- enhanced Penelope system will be completed to support all of VHDL and integrated with the Ada part of Penelope so that mixed hardware/software systems can be verified.

* Information listed above is at the time of submission. *

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