FRONT END SIGNAL PROCESSOR

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$55,481.00
Award Year:
1991
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
15789
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Athena Group Inc
3424 Nw 31st St, Gainesville, FL, 32605
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Glenn S Zelniker
Principal Investigator
(904) 371-2567
Business Contact:
() -
Research Institution:
n/a
Abstract
THE ABILITY TO MOVE C3 CAPABILITIES FORWARD (TOWARD THE SENSOR GROUPS) IN A DEFENSE SIGNAL AND IMAGE PROCESSING SYSTEM IS CRITICAL FOR TACTICAL AND LOGISTICAL REASONS. CURRENTLY, THE EXISTING TECHNOLOGY BASE IS INCAPABLE OF ACHIEVING THIS FUSION DUE TO SPEED, POWER, PACKAGING, AND POWER CONFLICTS. TO ACHIEVE A FRONT-END SIGNAL PROCESSING CAPABILITY, ATHENA PROPOSES TO EXPLOIT THE ADVANTAGEDS OF A HIGHLY PARALLEL ARITHMETIC SYSTEM CALLED THE RESIDUE NUMBER SYSTEM (RNS). IN THIS AREA, ATHENA HAS PROVEN CAPABILITES AND A HISTORY OF INNOVATION. THE INNOVATION TO BE STUDIED DURING THE PHASE I PERIOD IS CALLED THE A+ TECHNOLOGY WHICH EXTENDS ATHENA CURRENT STATE OF THE RNS-ART CHOSE TECHNOLOGY INTO A MULTIPLIER-FREE SYSTEM WHICH REQUIRES (FOR THE FIRST TIME) NO INTERNAL NUMBER SYSTEM CONVERSION. THE RESEARCH PROGRAM WILL DEVELOP THIS OPPORTUNITY AND VERIFY THE CONCEPT USING SIMULATION VIA PROGRAMMABLE GATE ARRAY DEVELOPMENT TOOLS. THE STUDY WILL QUANTIFY THE A+ SPPED, SPEED-AREA RATIO, RELIABILITY, AS WELL ULSI/WSI SENSOR INTEGRATION ADVANTAGED. THE PHASE I STUDY WILL DEVELOP A FRONT-END SIGNAL PROCESSING CAPABILITY BASED ON THE A+ TECHNOLOGY. THIS INCLUDES HIGH-DECIMATION RATE DIGITAL FILTERS (DECIMATION RATE OF 2(16) OR GREATER), SUPERIOR STEEP-SKIRT FIRS, MODULATORS/DEMODULATORS, AND HIGH-BANDWIDTH HILBERT FILTERS. ALL OF THESE OPERATIONS CAN BE FOUND AT THE SENSOR LEVEL OF A DEFENSE SIGNAL PROCESSING SYSTEM. DSP PERFORMANCE, AS WELL AS BANDWIDTH, AREA, AND POWER ESTIMATES WILL BE DERIVED FOR THE APPLICATIONS USING A+ AND CONVENTIONAL PROCESSOR TECHNOLOGIES. THE STUDY WILL PROVIDE THE FOUNDATION UPON WHICH A PHASE II PROCESSOR TECHNOLOGY WILL BE DEVELOPED IN CMOS ALONG WITH A SUPPORT INFRASTRUCTURE.

* information listed above is at the time of submission.

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