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Field Programmable Gate Array (FPGA) Physical Unclonable Functions

Award Information
Agency: Department of Defense
Branch: Office of the Secretary of Defense
Contract: W31P4Q-12-C-0133
Agency Tracking Number: O2-1194
Amount: $2,137,519.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: OSD10-A02
Solicitation Number: 2010.2
Solicitation Year: 2010
Award Year: 2012
Award Start Date (Proposal Award Date): 2012-05-14
Award End Date (Contract End Date): 2016-11-09
Small Business Information
P. O. 624 534 Lawrence Street, Moulton, AL, 35650
DUNS: 000000000
HUBZone Owned: N
Woman Owned: Y
Socially and Economically Disadvantaged: N
Principal Investigator
 James Lewis
 (256) 905-0775
Business Contact
 Terri Womack
Phone: (256) 905-0775
Research Institution
LIT accomplished all Phase I goals and technical objectives. In Phase I LIT produced an effective Random Number Generator (RNG) and tested two PUF designs. The PUF designs showed greatly improved Entropy and Stability over other technologies. LITs Entropy Goal for Phase II is 100% (already proven by analysis) and the Stability goal is one bit error per million bits. In Phase II LIT will mature this PUF technology by producing 3 programmable logic IP Blocks: Asymmetric PUF (APUF), Memory Authentication Parameter Sensor (LITs memory incorporating PUF), and a Random Number Generator. LIT partner Lockheed Martin Mission Systems and Signals will test the IP Blocks (Cores) in tactical hardware to achieve TRL 8. LIT will produce interface software to use with the PUF cores allowing a customer to access, test, evaluate, and characterize the PUF performance in their application. LIT is producing a PUF test suite to accumulate and process test results in order to quantify Variation, Entropy, and Stability metrics. At the end of Phase II LIT will provide two licenses for each PUF core and provide 2 day training on the use of the IP Blocks and related tools.

* Information listed above is at the time of submission. *

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